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CDB8422
2.5.2.3
AUX MCLK Source (AUX_Mclk)
Default = 0
Function:
This bit controls the source of the auxiliary MCLK signal. If the CS8422’s GPO3 pin is selected, the GPO3
pin should be configured to output XTI_OUT (CS8422 register 06h = XFh).
AUX_Mclk Setting
AUX MCLK Source
0 .......................................... Y4 Canned Oscillator.
1 .......................................... CS8422 pin 30 (GPO3).
2.5.2.4
CS8422 Reset Pin (DUT_RST)
Default = 1
Function:
This bit controls the state of the CS8422’s RST pin.
DUT_RST Setting
CS8422 Reset State
0 .......................................... CS8422 in reset.
1 .......................................... CS8422 out of reset.
2.5.3
Subclock Control (Address 03h)
7
TDM_SEL
6
Reserved
5
SAI_MS1
4
SAI_MS0
3
SAO2_MS1
2
SAO2_MS0
1
SAO1_MS1
0
SAO1_MS0
2.5.3.1
TDM Header Subclock Source (TDM_SEL)
Default = 0
Function:
This bit controls the source of the LRCK and SCLK signals sent to the TDM header J30.
TDM_SEL Setting
TDM HDR Subclock Source
0 .......................................... CS8422 OLRCK2/OSCLK2.
1 .......................................... CS8422 OLRCK1/OSCLK1.
2.5.3.2
SAI Subclock Source (SAI_MS)
Default = 00
Function:
These bits control the direction of the LRCK and SCLK signals between the SAI header J22 and the
CS8422. The CS8422’ SAI port should be configured in the appropriate master/slave mode.
SAI_MS Setting
SAI Subclock Source
00 ........................................ HDR J22 drives CS8422’s ILRCK and ISCLK inputs.
01 ........................................ CS8422’s ILRCK and ISCLK outputs drive HDR J22.
10 ........................................ Reserved.
11......................................... Reserved.
18
DS692DB2
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